1. Field of the Invention
The present invention relates to a display device and a driving method for the display device.
2. Description of the Related Art
Display elements each including a current-driven light emitting section, and a display device including the display elements are already known. For example, a display element including an organic electroluminescent light emitting section made of electroluminescence (may be abbreviated to EL) that is an organic material (hereinafter, may be called an organic EL display element) has attracted attention as a display element capable of emitting high-luminance light when being driven with a low-voltage direct current.
Similarly to liquid-crystal display devices, for example, even a display device including the organic EL display elements (hereinafter, may be called an organic EL display device) is known to adopt as a driving method a passive matrix method or an active matrix method. The active matrix method has the demerit that a structure becomes complex but has the merit that the luminance of an image is high. The organic EL display element to be driven according to the active matrix method includes, in addition to a light emitting section formed with an organic layer including a luminous layer, a drive circuit that drives the light emitting section.
As a circuit for driving the organic electroluminescent light emitting section (hereinafter, may be called simply a light emitting section), a drive circuit including two transistors and one capacitor (called a 2Tr/1C drive circuit) has been revealed in, for example, JP-A-2007-310311 (patent document 1). The 2Tr/1C drive circuit includes, as shown in FIG. 2, two transistors of a writing transistor TRW and a driving transistor TRD, and further includes a capacitor C1. Herein, the other source/drain region of the driving transistor TRD forms a second node ND2, and the gate electrode of the driving transistor TRD forms a first node ND1.
As seen from the timing chart of FIG. 4, pre-processing necessary to perform threshold-voltage canceling processing is executed during a period TP(2)1. Specifically, a first-node initialization voltage VOfs (for example, 0 V) is applied to the first node ND1 over a data line DTL via the writing transistor TRW put to an on state with a scanning signal sent over a scan line SCL. This causes the potential at the first node ND1 to become equal to the voltage VOfs. A second-node initialization voltage VCC-L (for example, −10 V) is applied from a power supply 100 to the second node ND2 via the driving transistor TRD. This causes the potential at the second node ND2 to become equal to the voltage VCC-L. The threshold voltage of the driving transistor TRD shall be a voltage Vth (for example, 3 V). The potential difference between the gate electrode of the driving transistor TRD and the other source/drain region (hereinafter, for brevity's sake, may be called a source region) thereof becomes equal to or larger than the voltage Vth. This brings the driving transistor TRD to the on state.
Thereafter, threshold-voltage canceling processing is performed during a period TP(2)2. Specifically, while the writing transistor TRW is retained in the on state, the voltage generated by the power supply 100 is switched from the second-node initialization voltage VCC-L to a driving voltage VCC-H (for example, 20 V). As a result, the potential at the second node ND2 is changed toward a potential obtained by subtracting the threshold voltage Vth of the driving transistor TRD from the potential at the first node ND1. In short, the potential at the floating second node ND2 rises. When the potential difference between the gate electrode of the driving transistor TRD and the source region thereof reaches the voltage Vth, the driving transistor TRD is brought to an off state. In this state, the potential at the second node ND2 generally takes on a value (VOfs−Vth).
Thereafter, during a period TP(2)3, the writing transistor TRW is brought to the off state. The voltage on the data line DTL is set to a voltage equivalent to a video signal {a video signal (a driving signal and a luminance signal) VSig—m for use in controlling a luminance attained by the light emitting section ELP}.
Thereafter, writing processing is carried out during a period TP(2)4. More particularly, the scan line SCL is driven to a high level in order to bring the writing transistor TRW to the on state. As a result, the potential at the first node ND1 rises up to the video signal VSig—m.
Now, c1 denotes the capacitance of the capacitor C1, and cEL denotes the capacitance of a capacitor CEL included in the light emitting section ELP. Further, cgs denotes the capacitance of a parasitic capacitor interposed between the gate electrode of the driving transistor TRD and the other source/drain region thereof. When the potential at the gate electrode of the driving transistor TRD is changed from the voltage VOfs to the voltage VSig—m (>VOfs), the potentials at both the ends of the capacitor C1 (in other words, the potentials at the first node ND1 and second node ND2) change in principle. Namely, a charge consistent with a change in the potential at the gate electrode of the driving transistor TRD (=potential at the first node ND1) is distributed to the capacitor C1, the capacitor CEL of the light emitting section ELP, and the parasitic capacitor between the gate electrode of the driving transistor TRD and the other source/drain region thereof. If the capacitance cEL is much larger than the capacitances c1 and cgs, a change in the potential in the other source/drain region of the driving transistor TRD derived from a change in the potential at the gate electrode of the driving transistor TRD (VSig—m−VOfs) is limited. In general, the capacitance cEL of the capacitor CEL of the light emitting section ELP is larger than the capacitance c1 of the capacitor C1 and the capacitance cgs of the parasitic capacitor of the driving transistor TRD. For convenience' sake, a description will proceed without consideration taken into a change in the potential at the second node ND2 derived from a change in the potential at the first node ND1. The timing chart for driving shown in FIG. 4 is completed without consideration taken into the change in the potential at the second node ND2 derived from the change in the potential at the first node ND1.
With the foregoing actions, the video signal VSig—m is applied to the gate electrode of the driving transistor TRD with the voltage VCC-H applied from the power supply 100 to one of the source/drain regions of the driving transistor TRD. Therefore, as shown in FIG. 4, the potential at the second node ND2 rises during a period TP(2)4. The magnitude of the rise ΔV in the potential (potential correction value) will be described later. Assuming that Vg denotes the potential at the gate electrode of the driving transistor TRD (first node ND1), and Vs denotes the potential in the other source/drain region thereof (second node ND2), as long as the magnitude of the rise ΔV in the potential at the second node ND2 is not taken into consideration, the Vg and Vs values are expressed by an equation and a statement presented below. The potential difference between the first node ND1 and second node ND2, that is, the potential difference Vgs between the gate electrode of the driving transistor TRD and the other source/drain region thereof acting as a source region is expressed by a statement (A) presented below.Vg=VSig—m Vs≈VOfs−Vth Vgs≈VSig—m−(VOfs−Vth)  (A)
Specifically, the potential difference Vgs derived from writing processing performed on the driving transistor TRD depends only on the video signal VSig—m based on which the luminance attained by the light emitting section ELP is controlled, the threshold voltage Vth of the driving transistor TRD, and the voltage VOfs with which the potential at the gate electrode of the driving transistor TRD is initialized. The potential difference Vgs has nothing to do with the threshold voltage Vth-EL of the light emitting section ELP.
Next, mobility correcting processing will be described briefly. Along with the foregoing actions, during writing processing, mobility correcting processing is performed to change the potential in the other source/drain region of the driving transistor TRD (that is, the potential at the second node ND2) according to the property of the driving transistor TRD (for example, whether the mobility μ is large or small).
As mentioned above, the video signal VSig—m is applied to the gate electrode of the driving transistor TRD with the voltage VCC-H applied from the power supply 100 to one of the source/drain regions of the driving transistor TRD. As shown in FIG. 4, the potential at the second node ND2 rises during the period TP(2)4. As a result, if the mobility μ permitted by the driving transistor TRD is large, the magnitude of the rise ΔV (potential correction value) in the potential in the source region of the driving transistor TRD increases. If the mobility μ permitted by the driving transistor TRD is small, the magnitude of the rise ΔV (potential correction value) in the potential in the source region of the driving transistor TRD decreases. The potential difference Vgs between the gate electrode of the driving transistor TRD and the source region thereof comes to be expressed with a statement (B) presented below in place of the statement (A).Vgs≈VSig—m−(VOfs−Vth)−ΔV  (B)
As described later, qualitatively, control should preferably be extended so that as the VSig—m, value gets smaller, the period TP(2)4 will get longer. JP-A-2008-9198 (patent document 2) has disclosed a constitution in which the trailing edge of the scanning signal is inclined in order to control the length of the period according to the value of a video signal.
Owing to the foregoing actions, threshold-voltage canceling processing, writing processing, and mobility correcting processing are completed. At the beginning of a succeeding period TP(2)5, the writing transistor TRW is brought to the off state with a scanning signal sent over the scan line SCL in order to float the first node ND1. The voltage VCC-H is applied from the power supply 100 to one of the source/drain regions (hereinafter, for brevity's sake, may be called a drain region) of the driving transistor TRD. Therefore, as a result, the potential at the second node ND2 rises. The same phenomenon as that occurring in a so-called bootstrap circuit occurs at the gate electrode of the driving transistor TRD, and the potential at the first node ND1 rises. The potential difference Vgs between the gate electrode of the driving transistor TRD and the source region thereof is retained at the value expressed by the statement (B). A current flowing into the light emitting section ELP is a drain current Ids flowing from the drain region of the driving transistor TRD to the source region thereof. Supposing the driving transistor TRD ideally acts at a saturation point, the drain current Ids is expressed by an equation (C) presented below. The light emitting section ELP emits light at a luminance consistent with the value of the drain current Ids. A coefficient k will be described later.
                                                                        I                ds                            =                            ⁢                              k                ·                μ                ·                                                      (                                                                  V                        gs                                            -                                              V                        th                                                              )                                    2                                                                                                        =                            ⁢                              k                ·                μ                ·                                                      (                                                                  V                        Sig_m                                            -                                              V                        Ofs                                            -                                              Δ                        ⁢                                                                                                  ⁢                        V                                                              )                                    2                                                                                        (        C        )            
According to the equation (C), the drain current Ids is proportional to the mobility μ. For the driving transistor TRD permitting a larger mobility μ, the potential correction value ΔV gets larger. The value of (VSig—m m−VOfs−ΔV)2 in the equation (C) gets smaller. Therefore, a variance in the drain current Ids derived from a variance in the mobility μ permitted by the driving transistor can be compensated.
The actions to be performed in the 2Tr/1C drive circuit that have been briefed previously will be detailed later.